Floating Point Design
R2026bWhen your model design uses Single or
Double data types, use native floating-point or FPGA
floating-point target libraries to generate synthesizable HDL code for your
Simulink® model. HDL Coder™ can map your design to the native floating-point library and a
vendor-specific FPGA point library, such as the Altera® or AMD® FPGA floating-point libraries.
Categories
- Native Floating Point
HDL Coder native floating-point, the various features supported, how to model your design, generate HDL code, and verify the generated code
- FPGA Floating-Point Libraries
Map to Altera and AMD FPGA floating-point libraries
Featured Examples
Floating Point Support: Field-Oriented Control Algorithm
In this example you review a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM) implemented using single-precision and half-precision floating-point types.
Design Model by Using HDL Coder Native Floating Point and Intel Hard Floating Point
Create a model design that uses both HDL Coder™ native floating-point (NFP) and Intel® hard floating-point (HFP) IP. Using the NFP and HFP blocks together in a mixed design offers better FPGA resource utilizations. For complex models, this mixed design allows you to have bigger design into the FPGA fabric.
Generate HDL Code Using HDL Coder Native Floating Point and AMD Floating Point Library IP
Create a model design that uses both HDL Coder™ native floating-point (NFP) and AMD® floating-point IP. You can use this mixed-design approach to accommodate larger and more complex designs into the FPGA fabric. You can use this hybrid design with AMD floating-point libraries on AMD devices such as Versal, Zynq® UltraScale+™, and more.
