HDL Applications for Communication Algorithms

Create and run HDL applications using Communications Toolbox™ and Wireless HDL Toolbox™ blocks

This section contains algorithms and HDL applications that you can develop by using blocks from Communications Toolbox and Wireless HDL Toolbox that are supported for HDL code generation. Wireless HDL Toolbox provides sample-based algorithms in Simulink^® for the design and implementation of 5G NR, LTE, and other wireless communications subsystems on FPGAs and ASICs. Communications Toolbox provides algorithms and apps for the analysis, design, end-to-end simulation, and verification of communications systems.

To filter the Simulink Library Browser to show only HDL-supported blocks in the Communications Toolbox and Wireless HDL Toolbox libraries, enter hdllib. For a filtered list of Communications Toolbox and Wireless HDL Toolbox blocks supported for HDL code generation, see Communications Toolbox Block List (HDL Code Generation) (Communications Toolbox) and Wireless HDL Toolbox Block List (HDL Code Generation) (Wireless HDL Toolbox).

Functions

hdllib Display blocks that are compatible with HDL code generation

Topics

Wireless Communications Design for ASICs, FPGAs, and SoCs
Design wireless communication algorithms for hardware by using Wireless HDL Toolbox blocks.

Featured Examples

HDL QPSK Transmitter and Receiver

Implement a QPSK transmitter and receiver in Simulink® that is optimized for HDL code generation and hardware implementation.

Open Model

HDL QAM Transmitter and Receiver

Use Simulink® blocks that support HDL code generation to implement a 64-QAM transmitter and receiver for HDL code generation and hardware implementation.

Open Live Script

Airplane Tracking with ADS-B Captured Data

Implement the Automatic Dependent Surveillance - Broadcast (ADS-B) receiver for HDL code generation and hardware implementation. This example decodes ADS-B extended squitter messages which can be used to track the airplane. The HDL-optimized model in this example uses Simulink® blocks that support HDL code generation to implement the ADS-B Receiver. This example model is used for real-time processing in HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 (SoC Blockset), which requires the SoC Blockset™ Support Package for Xilinx® Devices.

Open Model

Generate HDL Code for Viterbi Decoder

Two different modeling patterns to implement the Viterbi decoding algorithm and generate HDL code. One of the patterns uses a MATLAB Function block. The other pattern uses the Viterbi Decoder block. You need a Communications Toolbox license to use the Viterbi Decoder block.

Open Live Script