socExportReferenceDesign

R2026b

Export custom reference design for HDL Workflow Advisor

Syntax

socExportReferenceDesign(topModelName)

socExportReferenceDesign(topModelName,Name,Value)

Description

socExportReferenceDesign(topModelName) exports a custom reference design from an SoC Blockset™ for AMD model with name topModelName. To create an SoC Blockset for AMD model, you must perform one of these actions.

• Create a model using an SoC Blockset for AMD template. For more information, see Use Template to Create SoC Model (SoC Blockset).

• Open Simulink^®. On the Apps tab click System on Chip (SoC).

• In an existing Simulink model, click Model Settings in the Modeling tab. In the left pane, select Hardware Implementation. Then, set Hardware board to a supported SoC board. For a list of supported SoC boards, see Supported Third-Party Tools and Hardware (SoC Blockset).

Use this exported design with HDL Workflow Advisor (requires HDL Coder™ license). Use this function to eliminate the manual steps for creating a custom reference design, as described in Deploy IP Core on Custom Hardware (SoC Blockset). Use the exported reference design in the IP core generation workflow with the HDL Workflow Advisor. For more information, see IP Core Generation Basics (SoC Blockset).

For more information about the HDL Workflow Advisor app, see Getting Started with the HDL Workflow Advisor.

To use this function, you must first install Xilinx^® Vivado^® or Intel^® Quartus^®.

socExportReferenceDesign(topModelName,Name,Value) specifies options using one or more name-value pair arguments.

Examples

Export Custom Reference Design from SoC Model

Export a custom reference design from the soc_image_rotaion.slx model.

socExportReferenceDesign('soc_image_rotation')

Export Reference Design Using Specific Arguments

Export a custom reference design from the soc_hwsw_stream_top model.

• Exclude the DUT named "FPGA Algorithm Wrapper" from the reference design.

• Place the generated output in folder C:/Work.

• Generate a board definition file with board name "My ZC706 Board". This name appears in the Target platform menu in the HDL Workflow Advisor app.

• Generate reference design definition file with the design name My ZC706 Design.

socExportReferenceDesign('soc_hwsw_stream_top',...
    'DUTName','FPGA Algorithm Wrapper',...
    'Folder','C:/Work',...
    'TargetPlatform','My ZC706 Board',...
    'ReferenceDesign','My ZC706 Design')

Input Arguments

topModelName — Name of top Simulink model

character vector | string scalar

Name of the top Simulink model, specified as a character vector or string scalar. The reference design is exported from the topModelName model. This model must be an SoC Blockset for AMD model.

Example: 'soc_hw_sw_stream_top' specifies the model with name 'soc_hw_sw_stream_top'.

Data Types: char | string

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Example: socExportReferenceDesign('soc_image_rotation','Folder','refDesignFolder') exports a reference design from the model soc_image_rotation, and places the generated files in a folder named refDesignFolder.

DUTName — Name of DUT subsystem to exclude from reference design

inferred (default) | character vector | string scalar

Name of DUT subsystem to exclude from reference design, specified as a character vector or string scalar. When there is one DUT in the model, the function infers the DUTName and sets it as the name of the DUT in the model. You must specify this name-value pair argument when the FPGA model has more than one DUT.

Example: 'soc_image_rotation_fpga/ImageRotation'

Data Types: char | string

Folder — Folder location for exported reference design files

topModelName_refdesign (default) | character vector | string scalar

Folder location for the exported reference design files, specified as a character vector or string scalar. When not specified, the files are placed in a folder named topModelName_refdesign, where topModelName is the name of the model.

Example: 'C:/Work/refDesign'

Data Types: char | string

TargetPlatform — Name of target platform

same as SoC model (default) | character vector | string scalar

Name of the target platform, specified as the comma-separated pair consisting of 'TargetPlatform' and a character vector or string scalar. When you do not specify this value, the name of the target platform matches the Hardware Board parameter value in the SoC model configuration parameters. In the HDL Workflow Advisor tool, this target platform name appears as TargetPlatform (generated by SoC Blockset), where TargetPlatform is the value for this name-value pair argument.

Example: 'Xilinx Zynq ZC706 evaluation kit'

Data Types: char | string

ReferenceDesign — Name of generated reference design

topModelName model (default) | character vector | string scalar

Name of the generated reference design, specified as the comma-separated pair consisting of 'ReferenceDesign' and a character vector or string scalar. When you do not specify this value, the name of the generated reference design is topModelName model, where topModelName is specified by the input topModelName.

Example: 'My ZC706 Design'

Data Types: char | string

Version History

Introduced in R2020a