You can develop test scenarios by authoring input data, mapping external data to your test cases, or automatically generating inputs using Simulink® Design Verifier™:
Create a template MAT-file or Excel® file from your model and add values.
Place a Signal Editor block in the system under test and author inputs graphically.
Map MAT- or Excel files to the system under test.
Create a test directly from data contained in an Excel files. For more information, see Run Tests Using External Data.
Generate test inputs Simulink Design Verifier to extend coverage or replicate design error conditions. Add the generated tests to your test file.
You can also author test inputs that react to simulation behavior by using a Test Sequence block. Define sets of steps and transitions by using MATLAB® as the action language. You can use sequential or switched step groups in a hierarchy. Create test sequences in a Test Sequence block.
|Test Sequence||Create simulation testing scenarios, function calls, and assessments|
Use Simulink Design Verifier to generate tests that extend coverage and recreate design errors, and add generated tests to your test file.
Create and run an equivalency test to compare normal simulation and SIL/PIL code generation output.
Overview of test sequence actions, transitions, and hierarchy.
How to use test steps, transitions, data, and
sequences in the Test Sequence and Test Assessment
Operators and expressions used in Test Sequence and Test Assessment blocks and Stateflow® charts.
Transition between test sequence steps using conditional logic, temporal operators, and event operators.
Generate signal pattern inputs to the component under test, and call external functions from test steps.