How to solve Algebric loop error without adding delay.

Hi,

I'm designing a DSP system in simulink with the purpose of using fixed-point and HDL coder tool-boxes to convert it into FPGA synthesizable HDL afterwards. But one of the biggest issues I keep encountering is the Algebric loop error and I know the proposed solution is to break the loop with delays but that can break the implemenented algorithm in many cases.

For example if I want to use AXI4 protocol to communicate with a DDR memory using a state machine in a matlab function, Both sides of the transfer need to check both valid and ready (rd_dvalid, rd_dready) signals in the same cycle in order to know wheter they can do a valid transfer in that cycle or not. But this seems impossible because of the Algebric loop they create and hence, you need to add a delay in either valid or ready signal's path, meaning one is always one cycle behind the other.

If there is any way to workaround this issue feel free to mention it.

Thanks,

Ali

Answer 1

[Kiran Kintali]

HDL Coder supports various memory interfaces including AXI4 and DDR memory access.

https://www.mathworks.com/help/hdlcoder/ug/performing-large-matrix-operation-on-fpga-using-external-memory.html

It looks like you are using MATLAB Function Block to model some of these access patterns.

I wonder if this option (Use Nondirect Feedthrough in a MATLAB Function Block) in MALTAB Function would help your usecase

Can you reach out to support team on this issue?

[ALi Falahati]

Thanks, I will try this option out and see if it helps