import hdl coder fails, why?

I have the code below in verilog that implements cordic algorithm
`timescale 10 ns / 10 ns
module cordic_test
(
clk,
x,
y,
rst,
enable,
angle
);
input clk,rst,enable;
input [15:0] x,y;
output reg [15:0] angle;
reg signed [15:0] r,s,rnew,snew;
reg [4:0] i;
wire[0:15] tanLUT_fixed={16'h4000,16'h25c8,16'h13F6,16'hA22,16'h0516,16'h028B,16'h0145,16'h00A2,16'h51,16'h29,16'h14,16'hA,16'h5,16'h3,16'h2,16'h1};
always@(posedge clk)
if (!rst)
begin
rnew<=0;
snew<=0;
end
else if (enable==1)
begin
r<=x;
s<=y;
end
else begin
for(i=0;i<=15;i=i+1)
begin
if(s>0) // CW // Error: Multiple assignments on signal 'r' is not supported.
//Hdl Import parse failed.
begin
rnew<=r+(s>>i);
snew<=(s-(r>>i));
r<=rnew;
s<=snew;
angle<=(angle+tanLUT_fixed[i]);
end
else //CCW
begin
rnew<=(r-(s>>i));
snew<=(s+(r>>i));
r<=rnew;
s<=snew;
angle<=(angle-tanLUT_fixed[i]);
end
end
end
endmodule
. While importing through hdl coder, I get the error mesage "Multiple assignments on signal 'r' is not supported. Hdl Import parse failed. ". What could be wrong. Synthesizes well.

Respuestas (1)

Kiran Kintali
Kiran Kintali el 16 de Abr. de 2023

0 votos

This is a limitaiton of importhdl feature. In general only subset of verilog is convertible to Simulink using this feature.

2 comentarios

Gary
Gary el 16 de Abr. de 2023
What corrections need to be done in the code?
Kiran Kintali
Kiran Kintali el 17 de Abr. de 2023
What version of MATLAB are you using?
There is 128bit limitation for the import capability.
wire[0:15] tanLUT_fixed={16'h4000,16'h25c8,16'h13F6,16'hA22,16'h0516,16'h028B,16'h0145,16'h00A2,16'h51,16'h29,16'h14,16'hA,16'h5,16'h3,16'h2,16'h1};

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R2019a

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Preguntada:

el 15 de Abr. de 2023

Comentada:

el 17 de Abr. de 2023

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