HDL Coder Vivado timing report shows infinite slack

I'm using HDL coder to deploy a controller model in simulink onto Speedgoat FPGA, at the build bitstream stage i get a message saying 'Run build process passed with timing: Timing constraints met.'. But when i open the timing report, in the min delay paths section i see some paths with infinite slack? is this something that would affect the FPGA performance? If so how can i fix this?

Thank you in advance