I have designed a control system in Simulink and now I am trying to port the algorithm to a FPGA by using the HDL Coder (Matlab 2017b). The target is a Zedboard with the z-7020 SoC. The synthesis tool is Vivado (version 2016.4).
Within the design there are a few math operations, including the calculation of square roots. I used the square root block that can be found in the Simulink library (HDL Coder/Math Operations). Whenever I generate code and start the synthesis in Vivado, i receive critical warnings concerning timing loops (called "combinational loops" in the timing report). It appears that these are produced by the square root functions, as Vivado detects the loops in the generated source code of the square root functions. However, when I design a simple model that only includes sources that are connected to the square root blocks, no timing loops occur.
After the implementation of the actual control system in Vivado, the utilization of LUT, DSP etc. is below 80% for each category, so I assume it is not an issue of too little resources of the FPGA. For both cases, the simple model and the actual model have the same clock frequency.
Does anyone know why these critical warnings appear?