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使用Generate HDL Code from MATLAB Code Using the Command Line Interface时,显示错误使用 codegen

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shu yuan
shu yuan on 7 May 2019
按照help文档Generate HDL Code from MATLAB Code Using the Command Line Interface,结果显示错误使用 codegen 。
Input types not specified for design(s) 'mlhdlc_dti', inferring types by simulating the first test bench: 'mlhdlc_dti_tb' in the base workspace.
============= Step1: Analyze floating-point code ==============
============= Step1a: Verify Floating Point ==============
### Analyzing the design 'mlhdlc_dti'
### Analyzing the test bench(es) 'mlhdlc_dti_tb'
### Begin Floating Point Simulation (Instrumented)
### Floating Point Simulation Completed in 0.7895 sec(s)
### Elapsed Time: 1.1686 sec(s)
============= Step2: Propose Types based on Range Information ==============
============= Step3: Generate Fixed Point Code ==============
### Generating Fixed Point MATLAB Code mlhdlc_dti_fixpt using Proposed Types
### Generating Fixed Point MATLAB Design Wrapper mlhdlc_dti_wrapper_fixpt
### Generating messages during fixed-point conversion: mlhdlc_dti_fixpt_log.txt
### Generating Mex file for ' mlhdlc_dti_wrapper_fixpt '
Code generation successful: View report
警告: The expression 'yt = upper_limit' was not executed during simulation.
Consider using a more thorough testbench.
警告: The expression 'is_clipped = positive_sat_occurred' was not executed
during simulation. Consider using a more thorough testbench.
警告: The expression 'yt = lower_limit' was not executed during simulation.
Consider using a more thorough testbench.
警告: The expression 'is_clipped = negative_sat_occurred' was not executed
during simulation. Consider using a more thorough testbench.
Found some unsupported constructs during float to fixed point conversion. Please see the above error messages for details.
### Generating Type Proposal Report for 'mlhdlc_dti' mlhdlc_dti_report.html
===================================================
### Begin Verilog Code Generation
### Generating HDL Conformance Report mlhdlc_dti_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on mlhdlc_dti_fixpt as mlhdlc_dti_fixpt.v.
### Generating Resource Utilization Report resource_report.html.
### Begin TestBench generation.
### Collecting data...
### Begin HDL test bench file generation with logged samples
### Generating test bench data file: u_in.dat.
### Generating test bench data file: y_expected.dat.
### Working on mlhdlc_dti_fixpt_tb as mlhdlc_dti_fixpt_tb.v.
### Simulating the design 'mlhdlc_dti_fixpt' using 'ModelSim'.
### Generating Compilation Report mlhdlc_dti_fixpt_vsim_log_compile.txt
### Generating Simulation Report mlhdlc_dti_fixpt_vsim_log_sim.txt
### Simulation successful.
Error occurred when running post codegeneration tasks
### Generating HDL Conformance Report mlhdlc_dti_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 1 errors, 0 warnings, and 0 messages.
Coder:hdl:post_codegen: Error: failed to run post code generation tasks:
hdlcommon:workflow:DownstreamInvalidValue Invalid value "Xilinx ISE" for option "Tool"
Valid values for "Tool" are:
No synthesis tool available on system path;
MATLAB HDL Coder failed in the post code generation phase. See HDL Coder
conformance report.
Use help codegen for more information on using this command.
错误使用 codegen

Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 7 May 2019
It appears that you need to set up the path to ISE. See teh function hdlsetuptoolpath for information on how to do this.

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