HDL code generation from simulink and dumping process

I am using the 2016a and 2019b Matlab Simulink software for modeling my system. I have altera cyclone v and I want to dump my controller cording into it.

Please help me to generate the HDL cord and dumping process.

Answer 1

[Kiran Kintali]

The question is a bit vague; can you provide more specifcis on your workflow issues?

HDLCoder should support cyclone V workflow. I would recommend using latest version of HDLCoder to take advantage of the enhanced features.

https://www.mathworks.com/products/hdl-coder.html

HDL CoderTM generates portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.

HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture (49:42) and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.