System for defining and registering boards and reference designs.
Define the interface and attributes of a custom SoC board. After defining the board, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Define the interface and attributes of a custom SoC reference design. After defining and registering the reference design, you can target it using the IP Core Generation Workflow in the HDL Workflow Advisor.
Learn how to define custom parameters and custom callback functions for your custom reference design.
Learn how you can create an IP repository and add the IP modules in the repository to your custom reference design.
The following hardware is supported for the IP Core Generation workflow:
Synthesis ToolTarget Platform
- Xilinx VivadoZedBoard and with FMC-HDMI-CAM and FMCOMMS2/3/4/
- ZC706 and with FMC-HDMI-CAM and FMCOMMS2/3/4/ and FMCOMMS5
- ZC702 with FMC-HDMI-CAM
- Zynq ZC706 evaluation kit
- Zynq ZC702 evaluation kit
- PicoZed FMC-HDMI-CAM
- Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit
- Intel Quartus ProArria 10 SoC development kit
- Altera Quartus II
- Altera Quartus II refers to the synthesis tool Intel Quartus Prime Standard.
- Arria 10 SoC development kit
- Cyclone V SoC development kit Rev. C and Rev. D
- Arrow DECA Max 10 FPGA development board
- Arrow SoCKit development board
- Arria 10 GX FPGA development kit