I have been working on simulating HDL logic on simulink, I am trying to simulate a 32 bit counter @ 250Mhz clock rate. To achieve this I am using HDL optimized counter which allows me to set bits and sample time. I am setting world length to 32 bits and sample time as 1/250e6, I am using step size as 5000 and simulation stop time as 1 second. I am experiencing extremely slow simulation time and need assistance with that.
I understand that using such a big counter with extremely small sampling time would obviously make the simulation slower, but I am trying to find a work around to this problem.
How can I simulate this without significant performance loss?
Is there a way to simulate HDL in any other way?
Any suggetions would be extremely valuable.
Thanks in advance.