I'm trying to convert an enabled subsystem and function call generator to embedded for a embedded coder/hdl system. For both the systems to interact should I take the embedded coder parts out of the HDL coded blocks?
If your target hardware requires you to generate C and HDL code it is better to split your design into two subsystems or two models / model reference blocks (one for hardware and other for software). See this video for general guidance on such a workflow.
For subsystem targeting FPGA/ASIC you need to model the algorithm using HDL supported subset of MATLAB and Simulink constructs for HDL code generation.
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