I am using HDL coder to generate RTL from simulink model.
As you know, it is import to assign time-scale of port in simulink model, which defines the clock rate of one module.
However, in my design there will be multiple time-scale. Some module works under tsa, some module works under tsb. Usually, I would like to assign time-scale at the very begining of a signal path, while others will inherit from its previous point, until the time-scale is changed. At this time, I will assign a new time-scale at the begining of a new clock rate module.
My question is is there a way to report all the time scale of each modules? The aim is to verify if I give them the correct clock rate or the clock domain of each module is correct.
Thanks a lot!