Jonggab Kil, Intel
Today’s high speed SerDes design requires upfront effort by architects to allow for the direct extraction of an IBIS-AMI model from the architectural model. We demonstrate a process of creating an IBIS-AMI model from detailed characterization data of the CTLE, DFE, and CDR. The multi-stage CTLE is defined by frequency domain curves and saturating voltage in/out tables; poles/zeros extracted from the curves by vector fitting are combined with a memoryless nonlinearity to model each CTLE stage. Advanced impulse response equalization adaptation schemes quickly find near-optimum settings and serve as a starting point for custom adaptation implementations.
Recorded: 6 Nov 2019
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