From the series: FPGA Design with MATLAB
Raghu Sivakumar, MathWorks
Efficiently targeting an algorithm to FPGA or ASIC hardware requires adaptations to handle streaming data and to optimize the amount of fixed resources required. Simulink® helps visualize the hardware architecture and data flow. If your original algorithm was developed in MATLAB®, you can reuse much of that work as you use Simulink to adapt the algorithm for hardware implementation.
This video covers:
Welcome to the HDL Coder Video Series. In this video series we will learn a popular production proven path to take a MATLAB digital signal-processing algorithm through Simulink, Fixed-Point Designer, and HDL Coder to target an FPGA.
In the first part of the video series we discussed the strength of MATLAB and Simulink and provided an overview of the HDL Coder Self-Guided Tutorial available on the MathWorks File Exchange website.
In this part of the video series we will pay attention on implementing the Simulink model for the Pulse Detection Algorithm and compare it with the golden reference.
Before we create the Simulink model, run the pulse_detector_reference algorithm. This will initialize all the parameters in the MATLAB workspace, which we will pull into the Simulink model during the build.
To stream the data in the Simulink model, we will use the “Signal from Workspace” block which will stream the Receive Signal one sample at a time. The sampled data is passed through the discrete FIR Filter block with its coefficients referencing the CorrFilter variable. Enable logging of specific signals during the build stages of the Simulink model. We will utilize the logged signals to verify the output of the Simulink model with the golden reference algorithm.
To implement the hardware-friendly peak detector, use the raw sum of the square of the real and complex magnitudes since using complex operations such as square root will end up being resource expensive. To evaluate the magnitude squared, the signal is split into its real and imaginary components with the following blocks: Enable the signal Dimensions and Port Data, to visualize the data changes in Simulink.
To detect the peak, the Tapped delay block buffers the magnitude squared signal into 11 samples to create the sliding window
To implement the above peak detection, we will copy the “Hardware Friendly” algorithm in the Simulink model using the MATLAB Function Block.
Copy and paste the algorithm in the MATLAB function block. We will modify the algorithm to work with the buffered sample data and define the WindowLen Variable as a parameter.
This method enables to detect the pulse immediately, as this processes the data sample that follows the pulse as they arrive. In addition, this technique avoids storing the entire data sample in a fixed RAM. The parameter argument in the MATLAB function block takes the value from the MATLAB model workspace.
Clear the tunable option, WindowLen must be a constant expression for code generation purpose.
The middle sample in the stored 11 samples is compared to the other 10 to see if it’s the largest of the 11, and if so, if it’s larger than the threshold we specify. The threshold is the key for identifying the peak versus all the local ones as we slide the window.
The output of the peak detection implementation, signals “MidSample”
and “detected” are inputs to a unit delay enabled block, which will hold the peak value for display when the detected signal is TRUE. To visualize the outcome, connect a ‘Display’ block.
Using the test bench script ‘pulse_detector_v1’, we will run the output comparison of the MATLAB golden reference and the Simulink hardware implementation model. The comparison proves that the Simulink streaming model matches with the MATLAB reference, and the error is just the floating-point precision error.
In the second part of this video series on the HDL Coder, we have implemented the hardware implementation in Simulink and compared it against the MATLAB golden reference. We have also demonstrated the seamless interaction between MATLAB and Simulink environments during the Simulink model build.
In the next video we will prepare the Simulink model for HDL code generation.
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