How to Generate Implementation Metrics for a Wireless HDL Toolbox Block

The intellectual property (IP) blocks in Wireless HDL Toolbox™ are designed to generate efficient FPGA and ASIC implementations from HDL Coder™. However, different devices have different architectures and characteristics so you may want to assess a block's performance on your device. Learn how to estimate implementation metrics, as well as how to run an FPGA implementation and examine the relevant metrics from its reports.

Published: 14 Sep 2017

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