Hardware Implementation of High-Performance FFT Algorithms on FPGAs
DSP algorithms are challenging to implement on hardware, and hardware design engineers have little to no opportunity for design exploration. DSP HDL Toolbox™ helps engineers make design decisions early in the development cycle using pre-verified, hardware-ready Simulink® blocks that simulate hardware implementation of the algorithm. Using the fast Fourier transform block, learn:
- How to quickly change implementation options for low resource usage and latency designs
- How to change incoming streaming data from sample- to frame-based processing
- How to generate readable and synthesizable VHDL or Verilog using HDL Coder capabilities
Published: 22 May 2022
DSP System Toolbox is widely used by signal processing engineers to create behavioral reference models for hardware designs, for applications such as wireless communications, radar systems, and many more. Hardware engineers then need to interpret the specification document and hand-code an efficient hardware implementation, ensuring that throughput resource usage and power are within compliance of the requirements. Design decisions are made upfront regarding the implementation architecture. And in case of high-speed applications, the streaming data will need to be processed in frames.
Designing hardware implementations for DSP algorithms can be challenging. And this leads to engineers having limited design exploration opportunities. Using DSB HDL Toolbox library blocks, you can simulate hardware implementation of the algorithms. You can add these blocks in the reference behavioral model to simulate hardware latency, explore implementation options, and quickly change streaming data processing from sample to frame-based.
With the model representing the hardware implementation, you can use HDL coder to generate hardware optimize VHDL or Verilog code which is readable and synthesizable built for popular FPGA boards. Taking the Fast Fourier Transform block from the HDL Toolbox, learn how you can use the block parameters to quickly explore architecture implementation options and gigasample per second throughput rates when implemented on a popular FPGA board.
In this example, we will showcase two architectures of the FFT block using the Architecture parameter, using the Burst Radix architecture option for low-resource usage, as this architecture uses only one complex butterfly. And for low-latency design, utilize a Streaming Radix architecture. To explore frame-based processing, simply change the initialization function FrameSize, which you can access from the model properties.
Along with exploring the architecture and changing the incoming streaming data to frame-based processing, with HDL coder you can autogenerate VHDL or Verilog, and get the resource summary for supported hardware. Here, you can see the results for the earlier FFT design implementations that were run for a popular Xilinx target hardware.
DSP HDL Toolbox lets you explore hardware design implementations at higher level, assists in reaching design decisions in a more systematic method, and enables the transition from development to prototyping or production using the capabilities of the HDL coder. To learn more about the DSP HDL Toolbox visit the MathWorks product page.