What Is HDL Verifier?
Test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs with HDL Verifier™. Verify RTL with testbenches running in MATLAB® or Simulink® using cosimulation with HDL simulators. Use these same testbenches with FPGA and SoC development boards to verify HDL implementations in hardware.
HDL Verifier generates SystemVerilog verification models for use in RTL testbenches, including Universal Verification Methodology (UVM) testbenches. These models run natively in simulators from Siemens®, Cadence®, Synopsys®, and Xilinx® via the SystemVerilog Direct Programming Interface (DPI).
HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx, Intel®, and Microchip boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.
Published: 17 Feb 2012
HDL Verifier is an add on for Matlab or Simulink that lets you test and verify designs targeted for FPGAs, ASICs, and SoCs. Bugs are often introduced early in electronic design and not found until later. HDL Verifier connects your design specification to simulation and hardware-based testing and exports verification components to help find these costly bugs early.
Many projects will have system level simulations developed in Matlab and Simulink and components written in VHDL or Verilog. HDL Verifier's cosimulation can import this code, connect to an HDL simulator, and reuse your test benches to verify the design. You have access to the entire debug environment of the cosimulator, so you can investigate any discrepancies in the design.
You can also directly verify HDL implementations on FPGA hardware against your algorithms from within Matlab or Simulink with FPGA in the loop. You can apply data and test scenarios to the FPGA. And you can integrate existing HDL code with models under development in Matlab or Simulink. For debugging, you can probe internal signals in your design and set up triggers to capture data while it runs on the FPGA. Matlab allows read and write access to onboard memory locations and external DDR memories.
After you've simulated your design in Matlab or Simulink you can export components that plug into a system Verilog simulation environment. These can be analog or digital components. You can export a Simulink subsystem or Matlab function as C code with a DPI interface for system Verilog simulation.
If you don't already have a system Verilog environment, you can generate a UVM test bench from your Simulink model with HDL Verifier and Simulink Coder. This enables a direct transition from Simulink to the UVM environment. For more information, please visit the HDL Verifier product page on MathWorks.com.