This article introduces a Simulink® model that you can use as a basic framework for designing a wireless transceiver and building a wireless network. The wireless transceiver consists of a physical (PHY) layer and a medium access control (MAC) layer. The wireless network model is composed of multiple wireless transceivers communicating over fading channels.
We used a simple PHY, of QPSK modulation, and two selectable MAC layer protocols: ALOHA-based random back-off and CSMA/CA (IEEE 802.11). For simplicity, we omitted some blocks commonly found in wireless transceivers, such as interleaving, scrambling, and channel coding.
You can use the wireless transceiver model to study the behavior of the PHY and MAC, the interactions between the PHY and MAC, or the entire network. You can also use it as a template to design more complicated wireless transceivers, such as WLAN, V2X, and IOT by using algorithms and tools in Communications System Toolbox™, WLAN Toolbox™, and SimEvents™. Both the PHY layer blocks and the MAC layer Stateflow® charts enable you to generate HDL code with HDL Coder™ and target a real-time wireless transceiver implementation with the ADI RF SOM board containing SDR (AD9361) and FPGA (Xilinx® Zynq®-7000 SoC).
The top-level structure of the Simulink model consists of a fading radio network block and multiple wireless transceiver nodes (Figure 1). The nodes communicate in an ad hoc way: Any node in the network can transmit and receive signals to or from any other node. The wireless transceiver works in half-duplex mode. Within this network structure, the output of each transceiver node can reach all the inputs of the other transceivers. Following the principle of radio channel reciprocity, the two channels between any two nodes must have the same settings, while the channel settings of different wireless transceiver pairs can be different.
In the wireless transceiver design, the PHY layer is modeled with Simulink blocks close to the real hardware implementation. The MAC layer is modeled with Stateflow to reflect the nature of finite state machines in practice.
We'll now take a closer look at each component in the top-level Simulink model.
Packet Data Frame Format
The packet data frame format used in the wireless transceiver is the same as that defined in the MATLAB example Packetized Modem with Data Link Layer. As shown in Figure 2, the PHY Header has four fields, where Payload Length indicates the total bit length of the Data Link Unit, and it is covered by the Header CRC. The MAC Header has seven fields, where Frame CRC covers MAC Header and Frame Body. There are two frame types: a Data frame and an Ack frame. Ack frame has a zero Frame Body length. Both the Data frame and the Ack frame have a format like those defined in IEEE 802.11.
The wireless transceiver node model uses a half-duplex Tx/Rx mode (Figure 3). It consists of a PHY layer, a MAC layer, and a Logical Link Control (LLC) layer. The PHY layer has three main blocks: Transmitter, Receiver, and Tx/Rx Switch. All three are modeled in Simulink. The MAC and LLC layers are modeled with Stateflow charts to show the state transitions and logic operations occurring in the MAC and LLC layers of the wireless transceiver.
In the transmitter model of the wireless transceiver, the output TxOn controls the RF duplex switch for transmission or reception and the output TxSymbl streams out the modulated signal to the duplex switch during transmission (Figure 4). The input signals, TxDataOn and TxAckOn, control the transmission durations of the Data frame and the Ack frame, respectively. The Data frame and Ack frame are loaded in the lookup tables TxData_LUT and TxAck_LUT, respectively. Changing the variables in the LUTs changes the contents to be transmitted. The transmitter’s symbol rate is 10M symbols/sec and the bit rate is 20 Mbit/sec. If there is no symbol to transmit or the node is in receiving mode, TxSymbl is set to zero. The transmission and receiving pulse shaping filters are in the Tx/Rx Switch block.
The receiver of the wireless transceiver has three main function blocks: Signal Detection (SD), Decision Feedback Equalizer (DFE), and Demodulator and CRC (DCRC) (Figure 5). The SD block monitors the received signal power level. Once the power level exceeds the threshold, the SD block generates a signal to enable the DFE and DCRC blocks and starts feeding the received signal to DFE. The DFE is fractionally spaced, with two samples per symbol. The training reference preamble is stored in the REF_LUT block. The training data is recalled at the beginning of the training period of equalization. The DCRC block demodulates the equalized symbol stream to a bit stream, identifies the delimiter of the Payload Length field, and runs the header CRC to obtain an error-free payload length. Once the payload length is obtained, this block conducts the CRC operation for the payload, identifies the received packet as a Data frame or an Ack frame, and provides the frame type information to the MAC layer. If any CRC fails, the frame is dropped and the receiver reverts to a standby state.
The signal detector (SD), shown in Figure 6, is used to detect the signal arrivals to the wireless transceiver. The SD waveforms are shown in Figure 7. The absolute value of the signal is filtered by a two-stage exponential moving average filter. Once the output of the moving average filter exceeds the threshold, the detector generates the enable signal SigDe to start the DFE and DCRC blocks. The buffer block at the output SigOut generates the two-dimension (sample) data to the fractional DFE.
Decision Feedback Equalizer
The DFE in the wireless transceiver plays an important role. The functions of the DFE are to remove intersymbol interference (ISI), synchronize symbol timing, line up the frame field, and compensate for frequency offset , . As shown in Figure 8, the DFE operates at the symbol rate and takes two new samples for each iteration of equalizer weights.
Since the input dimension of the feedforward cell (DFE_Cell_FFW) is 2, each DFE_Cell_FFW block conducts the processing of two forward taps. Therefore, in the forward part of the DFE, 9 DFE_Cell_FFW blocks are used to implement the 18 forward taps. In the feedback part, each DFE_Cell_FBW has a one-dimension input and processes one feedback tap. Thus, the DFE has 6 feedback taps. The training length is set in the N-Sample Switch block in the DFE. The adapter weight scalar is set in the constant block named by “mu” in the DFE. Figure 9 illustrates the constellations before and after DFE.
Demodulator and CRC
The DCRC block (Figure 10) demodulates the equalized symbol stream from DFE to a bit stream. It then checks the header frame CRC and decodes the payload frame length. Once the payload frame length is obtained, the Payload CRC block in the DCRC starts. When the payload CRC is passed, the RxType Gen block checks the To Address field in the MAC Header. If the To Address field matches the address of the node, the block generates the RxDataOk or RxAckOk signals to the MAC layer according to the Type field in the MAC Header. Whenever a CRC fails or the address or data type is not appropriate, the frame is dropped.
The MAC conducts the intelligent control on the wireless transceiver. The MAC implements two selectable MAC functions: ALOHA-based (MAC_Sel=1) and CSMA/CA (MAC_Sel=0). The ALOHA-based MAC is straightforward, while the CSMA/CA MAC is more efficient.
For ALOHA-based MAC (Figures 11 and 12), when a node transmits a data frame, it expects to receive an Ack frame from the receiving node within the period defined by AckW. If no Ack is received in AckW, the MAC enters the random back-off procedure. The back-off procedure is iterated until either the Data frame is sent successfully or the maximum retry number is reached.
For CSMA/CA MAC (Figures 13 and 14), the medium must be quiet for the period of DIFS before transmitting, then the node starts the random Contention Window (CW) period. At the end of the CW, if the medium is still quiet, the node starts to transmit a Data frame; otherwise it waits for another quiet DIFS period. When the transmitting node hears an Ack frame within the SIFS period, it will transmit the next Data frame; otherwise it enters the DIFS period again.
Figure 15 shows the MAC layer structure with the two selectable MAC functions.
Logical Link Control Layer
The LLC layer handles the random data packets between the upper layer and the wireless transceiver (Figure 16). It generates randomly arriving data packets. For a long data packet, the LLC layer segments it into multiple data frames. The LLC layer also controls data frame queuing and monitors the data packet delivery status.
Results and Displays
The Simulink model described in this article has three wireless transceiver nodes that communicate in a round-robin fashion: Node 1 → Node 3 → Node 2 → Node 1. At each node, the arrival time of a data packet generated from the LLC layer is random. A data packet may have up to four data frames. The data frame payload length is set to 126 bytes. The system bit rate is 20 Mbit/Sec. The channel is modeled by a two-path Rayleigh channel mode with Doppler frequency spreading of 50 Hz and AWGN of 25 dB SNR (Eb/No).
In the ALOHA-based MAC (Figure 17), the three top plots are the transmission waveforms from the three nodes and the bottom plot is the value of the back-off counter of Node 1. In the figure, the signal with wider duration is a data frame and the one with a narrower duration is an Ack frame. Figure 18 shows similar plots for the CSMA/CA MAC.
From the results shown in Figures 17 and 18, we can draw the following conclusions:
- Collisions can happen between any two nodes or among all three nodes.
- A successful transmission is always followed by an Ack frame.
- Short turnaround time is important for high network throughput.
- CSMA/CA MAC is much more efficient than ALOHA-based MAC due to its use of carrier sense.
Figure 19 shows a zoomed-in view of the media traffic of the period from 2.8 ms to 3.4 ms. We can see that the Data frames Data1 and Data2 have collided, so neither Node 2 nor Node 3 can generate an Ack frame. After the waiting period of AckW, both Node 1 and 3 know that their Data frames did not go through. After a short back-off period, Node 1 resends Data1, and this time it goes through and receives an Ack from Node 3.
In this example, we built a Simulink model for a wireless network with multiple wireless transceivers and fading channels. The model is composed of Simulink blocks and Stateflow charts to demonstrate the efficiency of Model-Based-Design. The wireless transceiver has both PHY and MAC layers. The PHY layer model offers the basic functions of a generic PHY: modulation, demodulation, signal detection, synchronization, equalization, bitwise manipulation, header CRC, and frame CRC. The MAC layer model is made of Stateflow charts. It can use either the ALOHA-based MAC or the CSMA/CA (IEEE 802.11) MAC. This transceiver model also facilitates HDL implementation and SDR prototyping.
Having this model, we can study various behaviors of the wireless transceiver in the networking environment with respect to all system components. These behaviors may include:
- Fast sync, equalization, and turnaround
- Frame-based vs. sample-based processing
- Interactions between PHY and MAC
- Network performance with various channel models
By using additional function blocks in Communications System Toolbox, WLAN Toolbox, and SimEvents, you can extend this Simulink model to more sophisticated wireless transceivers, such as WLAN, V2X, and wireless IOT.