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Processor-in-the-Loop Simulation

Test generated code on target processor or simulator

A processor-in-the-loop (PIL) simulation cross-compiles generated source code, and then downloads and runs object code on your target hardware. By comparing normal and PIL simulation results, you can test the numerical equivalence of your model and the generated code. During a PIL simulation, you can collect code coverage and execution-time metrics for the generated code.

A PIL simulation requires a connectivity configuration.


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target.AddOnDescribe add-on properties for target feature class
target.APIDescribe API details
target.APIImplementationDescribe API implementation details
target.BoardProvide hardware board details
target.BuildDependenciesDescribe C and C++ build dependencies to associate with target hardware
target.CommunicationChannelDescribe communication channel properties
target.CommunicationInterfaceDescribe data I/O details for target hardware
target.CommunicationProtocolStackDescribe communication protocol parameters
target.ConnectionBase class for target connection properties
target.ConnectionPropertiesDescribe target-specific connection properties
target.MainFunctionProvide C and C++ dependencies for main function of target hardware application
target.PILProtocolDescribe PIL protocol implementation for target hardware
target.PortConnectionDescribe target connection port
target.ProcessorProvide target processor information
target.RS232ChannelDescribe serial communication channel
target.TargetConnectionProvide details about connecting MATLAB computer to target hardware
target.TCPChannelDescribe TCP communication properties
target.UDPChannelDescribe UDP communication
target.ApplicationExecutionToolCapture system command information to run application from MATLAB computer
target.CommandCapture system command for execution on MATLAB computer
target.HostProcessExecutionToolCapture system command information to run target application from MATLAB computer
target.SystemCommandExecutionToolCapture system command information to run target application from MATLAB computer
target.FunctionProvide function signature information
target.TimerProvide timer details for processor


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rtw.connectivity.ComponentArgsProvide parameters for each target connectivity component
rtw.connectivity.ConfigDefine connectivity implementation that comprises builder, launcher, and communicator components
rtw.connectivity.ConfigRegistryRegister connectivity configuration
rtw.connectivity.MakefileBuilderConfigure toolchain-based build process
rtw.connectivity.LauncherControl downloading, starting, and resetting of a target application
rtw.connectivity.RtIOStreamHostCommunicatorConfigure development computer communications with target processor
rtw.pil.RtIOStreamApplicationFrameworkConfigure target-side communications


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rtIOStreamCloseShut down communications channel
rtIOStreamOpenInitialize communications channel
rtIOStreamRecvReceive data through communication channel
rtIOStreamSendSend data through communication channel
rtiostreamtestTest custom rtiostream interface implementation
rtiostream_wrapperTest rtiostream shared library functions in MATLAB
piltestVerify custom target connectivity configuration for Simulink PIL simulation


targetManage target hardware information


SIL/PIL ManagerVerify generated code


SIL and PIL Simulations

An overview of software-in-the-loop (SIL) and processor-in-the-loop simulations (PIL).

Choose a SIL or PIL Approach

Test code generated from top models, referenced models, or subsystems.

Create PIL Target Connectivity Configuration for Simulink

Customize PIL simulation for your target environment.

Host-Target Communication for Simulink PIL simulation

Use the rtiostream API for communication between your development computer and target hardware during a PIL simulation.

Specify Hardware Timer

Specify a hardware timer using the Code Replacement Tool.

Set Up PIL Connectivity by Using target Package

Provide PIL connectivity between Simulink® and the target hardware.

Custom Toolchain Directives Required for Code Coverage and Execution Profiling

Specify compiler directives for building PIL application that supports code coverage analysis and execution profiling.

Configure and Run PIL Simulation

Set up and run top-model PIL, Model block PIL, and PIL block simulations.

SIL/PIL Manager Verification Workflow

A simplified workflow for verifying generated code.

PIL Simulation Sequence

How a PIL simulation proceeds.

Simulation Mode Override Behavior in Model Reference Hierarchy

How the simulation mode of the top model or parent model determines the simulation behavior of a model hierarchy.

Field-Oriented Control of Permanent Magnet Synchronous Machine

Simulate motor control system, generate controller code, and use PIL simulation to test numerical equivalence and profile code execution times.

Security for PIL Simulations

Security measures for PIL simulations.

SIL and PIL Limitations

Modeling and code generation features that are not supported or partially supported by SIL and PIL simulations.


View SIL and PIL Files in Code Generation Report

Produce a code generation report and static code metrics that cover SIL and PIL files.

Verification of Code Generation Assumptions

The SIL or PIL simulation checks code generation assumptions.

Featured Examples