HDL-Optimized System Design

Choose algorithms for wireless communications hardware system design

These blocks implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. The blocks use a streaming sample interface with a bus for related control signals.

Blocks

expand all

Error Detection and Correction

LTE Convolutional Encoder	Encode binary samples using tail-biting convolutional algorithm
LTE Convolutional Decoder	Decode convolutional-encoded samples using Viterbi algorithm
LTE CRC Encoder	Generate checksum and append to input sample stream
LTE CRC Decoder	Detect errors in input samples using checksum
LTE Turbo Encoder	Encode binary samples using turbo algorithm
LTE Turbo Decoder	Decode turbo-encoded samples
NR LDPC Encoder	Perform LDPC encoding according to 5G NR standard
NR LDPC Decoder	Decode LDPC code using layered belief propagation with min-sum or normalized min-sum approximation algorithm
NR Polar Encoder	Perform polar encoding according to 5G NR standard
NR Polar Decoder	Perform polar decoding according to 5G NR standard
Viterbi Decoder	Decode convolutionally encoded data using Viterbi algorithm
Depuncturer	Reverse puncturing scheme to prepare for decoding
Convolutional Encoder	Encode data bits using convolution coding — optimized for HDL code generation
Puncturer	Punctures data according to puncture vector
RS Decoder	Decode and recover message from RS codeword
RS Encoder	Encode message to RS codeword

Modulation

LTE OFDM Demodulator	Demodulate time-domain OFDM samples and return LTE resource grid
LTE OFDM Modulator	Modulate LTE resource grid and return time-domain OFDM samples
LTE Symbol Demodulator	Demodulate complex LTE data symbols to data bits or LLR values
LTE Symbol Modulator	Modulate data bits to complex LTE data symbols
NR Symbol Demodulator	Demodulate complex NR data symbols to data bits or LLR values
NR Symbol Modulator	Modulate data bits to complex NR data symbols
OFDM Demodulator	Demodulate time-domain OFDM samples and return subcarriers for custom communication protocols
OFDM Modulator	Modulate frequency-domain OFDM subcarriers to time-domain samples for custom communication protocols
FFT 1536	Computes fast-fourier-transform (FFT) for LTE standard transmission bandwidth of 15 MHz
OFDM Channel Estimator	Estimate channel using input data and reference subcarriers

Utilities

LTE Gold Sequence Generator

Generate Gold sequence

Featured Examples

Sample Rate Conversion for an LTE Receiver

Design and implement sample rate conversion for an LTE receiver front end. The model is compatible with the Wireless HDL Toolbox™ receiver reference applications, and supports HDL code generation with HDL Coder™.

Open Script

HDL Code Generation for Filtered OFDM (F-OFDM) Transmitter

Filtered OFDM (F-OFDM) applies a filter to the symbols after the IFFT in the transmitter to improve bandwidth while maintaining the orthogonality of the complex symbols. This example implements a transmitter F-OFDM for HDL code generation. The example shows how to go from a MATLAB® reference model to an HDL-optimized Simulink® model. It includes converting from double to fixed-point types, and minimizing the resource use of the design on an FPGA.

Open Script

HDL Implementation of a Variable-Size FFT

Implement a variable-size FFT using a single FFT core.

Open Script

Accelerate BER Measurement for Wireless HDL LTE Turbo Decoder

The workflow to measure the BER of the Wireless HDL Toolbox™ Turbo Decoder using parsim to parallelize the simulations across EbNo points. This approach can be used to accelerate other Monte Carlo simulations.

Open Script

HDL Implementation of AWGN Generator

The implementation of an additive white Gaussian noise (AWGN) generator that is optimized for HDL code generation and hardware implementation. The hardware implementation of AWGN accelerates the performance evaluation of wireless communication systems using an AWGN channel. In this example, the Simulink® model accepts signal-to-noise ratio (SNR) values as inputs and generates Gaussian random noise along with valid signal. The example supports SNR input ranges from –20 to 31 dB in steps of 0.1 dB.

Open Script

HDL Implementation of Digital Predistorter

The implementation of a digital predistorter (DPD) model that is optimized for HDL code generation and hardware implementation. The predistortion mechanism is executed in two stages. In the first stage, a set of DPD coefficients are estimated based on the input and output data of the power amplifier (PA). In the second stage, the input data of the PA is predistorted based on the estimated DPD coefficients and provided as new input to the PA. This example demonstrates a system-level simulation in which the DigitalPredistorter subsystem generates HDL code, while the DPD coefficient estimation generates C/C++ code. This example model supports only Normal and Accelerator simulation modes.

Open Script