Stateflow while-logic dead loop

I'am using stateflow to model a system.

With this logic i am expecting if the input is 1, the output should be 1. If the input is not 1, do nothing (it'a one-time logic, if the input is once not 1, the output will be none from then).

I used a step signal from 1 to 2 as an input. But the simulation can't proceed since its a dead loop at first time step. Why is that and how to solve this?

[VBBV]

Try using a continuous signal instead of step signal

[Dingxin Wang]

yes i tried to use a signal builder to build a continuous signal but it still didnt work

Answer 1

[Fangjun Jiang]

When input==1, you do have an infinite loop, right?

Connecting the feedback transition to the bottom junction would resolve it.

[Dingxin Wang]

hi, i dont really understand the infinite loop here. In the loop there is a precondition (input == 1), when the input changes to 2, it should jump out of the loop. How can i understand this?

[Fangjun Jiang]

See this for Stateflow while-loop. You don't have anything to change the condition. Any time when input==1, it will fall to the infinite loop trap.

https://www.mathworks.com/help/ecoder/ug/while-loop.html