About HDL simulink coder

Dear friends, I have an error when I try to convert StateFlow Block to Verilog: * Failed network:propagateClockRate:ratesDontMatch: When propagating rates on , signal *

Anybody can help me!

Thanks you so much!

Pham Van Dung

Answer 1

[Kiran Kintali]

Hi Pham,

Can you send me the model that reproduce the failure? thanks.

[e-mail]

[Pham Van Dung]

Ok. Many thanks! I've already fix this error!

[Srinivas Kartik Angadi]

how did you fix this?

[Pham Van Dung]

@Srinivas Kartik Angadi, I can't remember exactly. It has been 5 years. But may be the problem is the synchronization of the subsystem inside the stateflow block which I want to convert. I am sorry

Answer 2

[imane RGUIB]

Hello, Pham Van Dung and Kiran Kintali, I have the same error while trying to make an IP core generation of my design, comprising a stateflow chart, using the HDL workflow advisor:

Could not apply model's setting to the Target Interface Table in Task 1.2 of the HDL Workflow Advisor for the following reason:

network:propagateClockRate:ratesDontMatch: When propagating rates on <Network CtxName="slaveV2" RefNum="n1" UserName="slaveV2/SlaveI2C/Chart" RTTIClass ="class pir::Network"/>, signal <Signal CtxName="slaveV2" RefNum="s0" UserName="scl" RTTIClass ="class pir::Signal" Network="n1\> had rate 0.000000, while the trigger signal had rate 0.100000

Can you please tell me what can be the problem?

Thank you very much

[Pham Van Dung]

Hello there,

I did not remember exactly, but it seems to come from the reason that I used many clock cycle in the same block. For instance, in my Matlab code which is SVPWM for current control, there are two clocks: 200ns and 100 ns for this block.

Best,