Verify Xilinx RFSoC Gen-3 System Performance in mmWave Applications with MATLAB and Simulink - MATLAB & Simulink
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    Verify Xilinx RFSoC Gen-3 System Performance in mmWave Applications with MATLAB and Simulink

    Matt Brown, Avnet

    Overview

    In this webinar, engineers from Avnet and MathWorks will demonstrate Ethernet-based connectivity to MATLAB and Simulink that will allow you to capture, measure, and characterize RF performance with the Avnet Zynq UltraScale+ RFSoC Development kit.

    Highlights

    During our presentation, we will demonstrate how to:

    • Define RF test criteria for RFSoC
    • Connect to RFSoC hardware from MATLAB and Simulink
    • Analyze captured data to characterize board performance

    About the Presenter

    Matt Brown is an engineer at Avnet. His passion is to reduce the complexity of SoC design, allowing engineering teams to start development at the application level. Matt spent over a decade as an FAE, and also helped design Motorola's first Iridium™ satellite phone. Recent endeavors include Simulink-based workflows for software-defined radios and industrial drives.

    Noam Levine works in Technical Marketing at MathWorks, concentrating on hardware-targeted, application-based workflows. Noam holds a MSEE from Northeastern University and a BSEE from Boston University.

    Recorded: 29 Sep 2020

    Hi, and welcome to our presentation verify Xilinx RFSoC Gen-3 system performance in millimeter wave applications with MATLAB and Simulink. My name is Noam Levine from MathWorks and I'm joined today by Matt Brown from Avnet.

    Before we begin there's a couple logistics things I want to walk through. If you have any problems hearing the audio or seeing the presentation, please contact the webinar host by typing in the chat panel. If you have any questions for the presenters, you can type them in the Q&A panel on your webinar screen. These questions will be answered at the end of the presentation.

    In today's webinar we're going to start by having Matt go through a millimeter wave system development example. I'll then do a brief overview of RFSoC Gen-3 and talk about development workflows with MATLAB and Simulink for RFSoC starting with system modeling going through deployment. I'm then going to turn it back over to Matt.

    And he's going to talk about characterizing RFSoC Gen-3 performance with RFSoC Explorer starting with device level models and control, moving up to system level examples, looking at 5G g test models, and then talking about some hardware platform options for RFSoC. I'll then close things out and talk about some next steps that you can take to get started with developing systems for RFSoC with MATLAB and Simulink. And now I'll turn it over to Matt to walk you through the system development example.

    Thanks Noam. Let's start by describing the application space that we'll be addressing. Sub 6 gigahertz frequency bands are crowded. 5G FR2 opens up spectrum between 24 and 52 gigahertz. The challenge with these millimeter wave lengths is high propagation loss. So we need to deploy antenna arrays and use beam forming techniques to provide high spatial processing gain.

    One efficient architecture, known as hybrid beam forming, combines digital techniques with analog beam forming ICs. This type of system requires multiple channels of data conversion and high performance real time processing in a compact footprint. The third generation of Xilinx RFSoC provides up to 16 by 16 channels of giga sample data conversion. So really it's an ideal candidate for this type of system.

    Now of course, what you'd like is to just open MATLAB and start streaming waveforms to the chip. More practically, we start with the RFSoC Gen-3 ZCU208 development board and add an RF card providing conversion to millimeter wave.

    And here's what the system looks like on the bench. I have an application written in MATLAB talking to the ZCU2 await development kit over ethernet. The black dotter card on the right converts from 6 gigahertz up to the 20 to 30 gigahertz range. The application that we've written in MATLAB is called RFSoC Explorer.

    I'll start by opening up one of the DAC tiles and you can see here two channels are available within this DAC tile. Start by configuring a CW tone at 10 megahertz. And you can see it here shown in the time series plot down in the bottom right. Can switch over and look at this in the frequency domain as well.

    You can see that all the parameters of the data converter subsystem are available here for a convenient configuration including interpolation and CO mixer and other parameters of the DAC itself. I also have the ability to generate and import signals from other sources.

    Signal source for the bottom channel comes from the wireless waveform generator. This is a 5G NR signal and FR 2 spectrum. And you can see the frequency domain plot here in the right. Another convenient way to configure the DAC subsystem is by using the RFSoC Explorer built in APIs.

    Here I've created a structure of mixer settings and I can use the RFSoC Explorer built in API for configuring the mixer. And you'll notice back in the user interface, those changes are reflected. Here we use the API to change the channel 2 mixer to switch to course mixing by fs over 2. For data acquisition with the ADCs the tile structure looks similar, though there are a number of unique parameters here.

    And just like with the DAC we can use programmatic access to capture buffers of data. Here I've used the read ADC buffer API and stored the output in a variable called ADC buffer. The captured sample buffer is here in the MATLAB workspace ready for time domain or frequency domain analysis. Of course, you could also feed these further into other models that you might have.

    We'll explore some of the more advanced features of RFSoC Explorer later in this webinar. For now I'll turn it back over to Noam.

    Thanks Matt. Now I'd like to do a brief overview of what RFSoC is and where it fits in wireless applications. So RFSoC is part of the Zynq family of systems on chip and it's officially called the Zynq UltraScale+ RFSoC. And Zynq is a family of devices that has been supported by MathWorks since 2012.

    The third generation of RFSoC, which is what our examples will be based on, integrates 8 or 16 channels of RF data converters in an SOC architecture and supports all sub 6 gigahertz wireless applications. The RFSoC family is designed for high performance RF applications including 5G communications, radar, test and measurement equipment, and massive MIMO and hybrid beamforming applications.

    Combining RF and programmable logic on a single chip presents a unique design environment for engineers who may be used to working with discrete RF plus baseband processing components. And questions may arise about the quality of the RF signal in an integrated device.

    To address some of the requirements of developing algorithms in an integrated RF plus processing environment, we'll now highlight the steps of the system design process in MATLAB and Simulink. This design process encompasses system modeling and simulation, hardware evaluation and characterization, over the air testing, algorithm validation, SOC system modeling, and finally, hardware deployment. Matt will then dive into the hardware evaluation and characterization process in more detail.

    MATLAB and Simulink give you the capability to model and simulate your entire RF system. From behavioral models of physical RF devices, through models of antennas and transmission channels, having an accurate representation of the total system lets you build better algorithms faster.

    Once we understand the system in which we'll be working, the next step is to make sure our RF hardware will meet its performance requirements. In this development stage we generate wave forms in MATLAB and Simulink, send them out through our hardware, then loop the signals back into our hardware and analyze the return signals in MATLAB to determine hardware performance for a variety of standards based or custom wave forms.

    Once device performance is determined, we can extend our testing to verify that we can transmit signals over the air correctly. Using the same library of waveforms available in MATLAB and Simulink, we now add external test equipment into the mix which we can control from MATLAB. To validate that our baseband algorithms will work in the real world, using our RF SOC hardware to capture signals we can stream data into MATLAB and Simulink for processing and analysis.

    This stage allows us to explore multiple what if scenarios and algorithm options before committing any of them to hardware. Allowing you to focus your prototype development efforts on the algorithms that will likely yield the best results.

    In addition to confirming that our algorithms are numerically correct, we need to know if they will run correctly on a given SOC device. This stage of development allows you to test different algorithm partitioning options between the processing system and programmable logic of the Zynq UltraScale plus RFSoC, experiment with different buffer and FIFO sizes, and validate that not only will the results be accurate but that the algorithm will execute properly on the device.

    Now that we have determined that our hardware meets operating requirements, validated that our algorithm is numerically correct and ensured it can operate in real world scenarios, and determined that our algorithm can run within the allotted hardware resources, we're now ready to deploy our algorithms to the programmable logic and processing system of RFSoC and let it do the processing.

    With a guided workflow advisor, even those engineers not familiar with FPGA programming tools can generate HDL IP cores and embedded C code and employ them on RFSoC hardware. Once deployed, we can verify the operation through code simulation and FPGA in the loop testing.

    The remainder of this presentation is going to focus on hardware evaluation and characterization. So I'll turn it back over to Matt and he can walk through the details of RFSoC Explorer and the Avnet wideband millimeter wave radio development kit.

    Xilinx RFSoC architecture includes built in digital front end for each channel. And this includes digital up and down converters, digital mixers with local and NCOs, gain and phase compensation, as well as internal RFPLLs. Characterisation of the data converter subsystem is typically done with a careful frequency plan for the entire radio. We used MATLAB in Simulink to model the entire Gen-3 RFSoC digital up converter chain of half band filters.

    The expanded interpolation architecture and coefficients of Gen-3 silicon are not yet publicly released. So the graphic here shows our model for Gen-2 devices just to convey the idea. However, we did integrate accurate simulation models of the digital up converters for Gen-3 silicon in RFSoC Explorer.

    Since we're modeling the entire digital up converting chain in RFSoC Explorer, you can see the expanded interpolation range for Gen-3 silicon, 2x all the way up to 40x. And as we make changes here you can see the changes reflected in the frequency domain plot here on the right.

    Now what you're seeing here is the baseband signal and frequency domain. In order to see the output at the end of the digital up converting change we switched to duck output mode. Now there's the entire range that we would expect to see at the output of the duck, including the interpolation stages.

    Gen-3 RFSoC has built in image rejection filters for selecting either the high or low images in the frequency domain. So here selecting our low pass. You'd expect to see our signal at baseband unaffected. And that's what we see. And then selecting IMR high pass. You can see the effects. Our signal at baseband is massively attenuated in favor of the higher image.

    Our MATLAB model for the digital up converting chain includes the NCO mixer. This allows you to do careful frequency planning. For millimeter wave systems frequency planning and modeling is critical because once the signal passes through nonlinear RF analog components like amplifiers and analog mixers and finally arrives at test equipment, it's extremely difficult to de-embed the spurs introduced into the transmitted signal and diagnose root cause.

    So here within RFSoC Explorer you can experiment with different frequency plans. Here I'll mix our signal up to a frequency of 2000. And you'll see that reflected here in the frequency domain. Now, as you work with multiple channels in RFSoC Explorer you might want to see the output in an aggregate view.

    Here you could look at the DAC multi plots tab and keep track of the different wave forms across all tiles of all DACs. And within here just built in widgets for doing zoom functions, if you want to zoom in and look at a signal. And then you can export these as PNG graphic files for documentation.

    Also, if you'd like to start using some of the built in tools for analyzing things in the frequency domain, you can easily turn on spectrum analyzer. And this is the native MATLAB spectrum analyzer object with all the built in tools for doing channel measurement and signal analysis.

    The frequency plan for the Otava millimeter wave transceiver card was made to enable a range of wideband applications. So the RF range is roughly 20 to 30 gigahertz. There are independent low gloss letters for TX and RX locked to the same reference clock used for the RFSoC converters. And the architecture is flexible to allow high or low side LO injection.

    And you can see in the diagram that each RF signal chain includes gain and attenuator stages. Now the thing to note here is that these are high performance, off the shelf components that must be controlled. And we built that control into the RFSoC Explorer interface.

    Every component on the Otava DTRX2 millimeter wave card can be controlled from this tab within RFSoC Explorer. So you can see this independent power up for TX. Independent power up for RX. And each signal chain, both transmit and receives, can be independently controlled.

    We've also created an intuitive API to control all of the features you see here from the MATLAB command prompt. Here I've created a script that uses the API to iterate through several DSA settings in the transmit chain. And you can see, as we iterate through these values with the script using the API the changes are reflected here in the user interface.

    We've referenced 5G and our wave forms several times so far. As part of the standardization process, 3GPP has defined several types of reference waveforms to be used as the basis for tests such as throughput and EDM. MathWorks 5G tool box provides compliant wave forms for test models and reference measurement channels.

    The white paper shown here was authored by MathWorks 5G experts and is an excellent introduction to the topic. In RFSoC Explorer we access the 5G tool box by way of the wireless wave form generator. Here, we can select 5G test models and configure them for different use cases.

    We'll start by selecting FR2 for the 24 plus gigahertz range. In our first test model we'll select a single physical resource block at 64 gram modulation. We can also select a full band test model to test throughput. Here, we'll choose sub carrier spacing of 120 kilohertz and maximize our band width up to 400 megahertz, and generate the waveform.

    From here, we can directly export this wave form into RFSoC Explorer. You'll notice here the option to resample the signal into the sample rate domain of RFSoC Explorer. And that's all we have to get the 5G wave form into RFSoC Explorer.

    And then of course we can configure the target, that's RFSoC on the ZC208, and download this wave form directly into the DAC buffers for replay. Our goal was to demonstrate how this platform allows a system architect to easily configure the RFSoC data converter subsystem using an intuitive interface called RFSoC Explorer.

    Because the application is built on MATLAB, you have the ability to natively perform analysis, develop algorithms, and create simulation models that interact with streaming data. The prototype capabilities extend beyond RFSoC with RF front end cards, enabling over the air testing and radio in the loop experiments.

    If you'd like to try RFSoC Explorer, it's a free install from the MATLAB add-on store. Just click Get add-ons from the top ribbon and type RFSoC in the search box.

    The wideband millimeter wave radio development kit for RFSoC Gen-3 will be available in November of this year, 2020. Price is just below 20,000 US dollars. And if you'd like more information, go to the Avnet site and use the short URL rfsoc-mmw.

    In order to provide a path toward production with RFSoC Gen-3 devices, we're developing an XRF 8 module. This is production ready 8 by 8 direct RF sampling module with six gigahertz of analog bandwidth. It features the Gen-3 ZU47 or 48 device and features ultra low jitter RF PLLs and requires only a single input in the range of 5.5 to 16 volts.

    This will be available in Q1 of next year. If you'd like more information about this module, go to the Avnet site and use the short URL rfsocsom. And there will be a form there that you can put your name and email address into to request more information.

    In order to accelerate development on the XRF8 module RFSoC Explorer will include support for the module and a carrier card that launches early next year. Back to you Noam.

    Thanks Matt. Now I'd like to highlight some next steps if you're interested in learning more about system development for RFSoC Gen-3 from MATLAB and Simulink. To request a free MATLAB trial package and to learn more about the products behind the workflows we described earlier in this video, please visit mathworks.com/rfsoc.

    To learn more about wireless solutions in general from MATLAB and Simulink, you can visit mathworks.com/wireless, where you can take a look at some of our new ebooks for deploying 5G, and our wireless communications on FPGAs, along with information on wireless reference designs for 5G and other standards.

    Finally, if you'd like more individual information, you can just send us an email at rfsoc@mathworks.com. This brings us to the end of our presentation. We'll now take some time to answer your questions. If you have questions, please post them in the Q&A panel. We're going to take a few minutes to review them and then come back online to answer your questions.

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